Hardware
RV32I CPU Core
A five-stage pipelined RV32I CPU I built from the RISC-V spec in SystemVerilog, running on an FPGA at 71 MHz.
I built a RV32I CPU from the RISC-V spec in SystemVerilog. It runs on an Arty A7-100T at 71 MHz and talks to my computer over UART at 115,200 baud.
It’s a five-stage pipeline (fetch, decode, execute, memory, writeback) with a modified Harvard architecture. Most of the work was hazard handling. The core forwards results between stages so instructions don’t have to wait, stalls a cycle when an instruction needs a value that’s still being loaded, and flushes instructions when a branch or jump is taken. The decoder treats every instruction as illegal unless it’s explicitly recognized.
I verified each stage with its own testbench. The ALU passed 22,085 checks with no failures, and the design meets timing at a 14 ns clock period.
Next, I want to build a GPU.